Digital circuits may contain millions of devices on a single integrated circuit. The devices are generally very small to increase speed, reduce energy consumption and reduce the total area of an integrated circuit. Sometimes, an internally generated signal has to drive a very large external load as quickly as possible, such as when an internal signal has to drive an input/output pad of the integrated circuit. The internal signal is generally provided by a very small device that cannot drive a large load without incurring substantial delays due to the limited drive current available for charging/discharging the capacitive load.
The best performance in terms of minimum delay when an internal signal has to drive a large load may generally be achieved by using a chain of inverters, where each inverter is proportioned to the preceding inverter by an amount equal to the ratio of the final load divided by the input load (CL/Cin), otherwise commonly known as the electrical step-up, and this ratio is taken to the root power of the number of stages used in the chain. The number of stages in the chain is generally chosen such that this result is greater than e (about 2.7) but less than e2 (about 7.3).
In some circuits, such as a pipeline stage of a processor, use of optimally sized inverters may not be sufficient to meet timing constraints. This may be true when the pipeline stage is having trouble meeting timing constraints. Generally, latency is the time delay from when an input of a device changes state to when the output of the device changes state. Latency is generally measured from the 50% point of the input signal transition which caused the output to change, to the 50% point of output signal transition. Thus, what is needed is a circuit that boosts performance of logic gates with respect to latency and also reduces power consumed by the logic gates and/or area consumed by the logic gates.